Usage of PS region of ZYNQ Architecture

The XSA file contains HW Platform information generated by the Vivado project, and SW development is conducted, based on this information on Vitis.

Create a “Hello World” project in Vivado

Then click “Create Block Design” on the “IP INTEGRATOR” tab.
(In this example, we will only have serial communication between the PC and Zynq’s PS area (Uart), so we will not create a Design Source.)

Set the name of the block design.

Click the ‘+’ button (Add IP) in the right-hand diagram window,

Select ‘ZYNQ7 Processing System’.

Then the IP of Zynq’s PS is added.

In this example, Only the Uart peripheral of Zynq PS is used.

Select ‘MIO Configuration’ and check UART1 and set ‘Bank 1 I/O Voltage’ to ‘LVCMOS 1.8V’.

The MIO Configuration (Multiplexed I/O Configuration) determines whether each pin of the FPGA and the I/O peripheral are routed.
(Each pin of the FPGA can be connected to several I/O peripherals through a multi-plexer.)

Looking at the picture below, it can be seen that the UART1 to be used in the example is MIO48 and MIO49.

Referring to the circuit diagram of the Zybo z7 board, the bank voltage of the corresponding MIO is VCC1V8.
This means that the operating level of the MIO is 1.8 V.
Therefore, UART can operate normally only when ‘Bank 1 I/O Voltage’ is set to ‘LVCMOS 1.8V’.

Now, Remove unused parts from Zynq PS.

(1) Uncheck ‘M AXI GP0 interface’ in ‘PS-PL Configuration’.

(2) Uncheck ‘FCLK_CLK0’ in ‘Clock Configuration’.

Clock can be generated in the PS region and supplied to the PL region, but in this example, the PL region is not used, so the corresponding part is unchecked.

If you press OK, you can see that ZYNQ7 PS is simpler than before as follows.

Click ‘Run Block Automation’ in the upper left corner,

It may be seen that the interface (Fixed_io) is automatically set externally. (UART peripheral to MIO48, MIO49)

Press OK, and press ‘Validate Design (short key: F6)’ on the following screen.

Since this block diagram file is not a Verilog HDL file, it must be converted to a Verilog HDL file by ‘Create HDL Wrapper’.

Click “Create HDL Wrapper”.

Then Press ‘Okay’,

The HDL file is then created as follows.

Press ‘Generate Bitstream’ to create a Bitstream file with the corresponding HDL file.

Once the Bitstream file is created, select “File – Export – Export Hardware” to extract the XSA file.

When the Export Hardware Platform window appears, select Next.

If the ‘Include bitstream’ option is selected, Bitstream files can also be programmed into the FPGA on Vitis.

Set the name of the XSA file, select Next, and select Finish in the last window.

Then, it can be confirmed that an XSA file called ‘HelloWorld_XSA’ has been created in the HelloWorld project.

Now, Create a project in Vitis.

Run Vitis, specify the workspace path.

When Vitis runs, click ‘Create Application Project’.

The following figure describes the process of loading an HW Platform (XSA file) generated by Vivado and developing SW on Vitis based on that Platform.

When you press Next, a window appears where you can select a platform, but the platform you currently have does not exist.

Load the XSA file from “Create a new platform from hardware (XSA)”.
(Create a Vitis Platform based on the hardware described in the XSA file.)

Select the XSA file generated by Vivado’s HelloWorld project.

The XSA file is then loaded as follows.

Set the Application Project Name.

Zynq’s ARM Cortex-A9 consists of a dual core, but in this example only one core will be used.

Select ‘ps7_cortexa9_0’ and press Next.

Since it does not use any OS, the Operating System selects ‘Standalone’.

In Vitis, there is a template that is basically provided as follows, and in this example, the ‘Hello World’ template is used.

When you press Finish, a Vitis project containing ‘helloworld.c’ is created as follows.

Modify the main statement of ‘helloworld.c’ as shown in the picture above, and proceed with Build.

For serial communication between PC and Zynq, open ‘Vitis Serial Terminal’ with the search function in the upper right.

The ‘Vitis Serial Terminal’ is created in the lower right, and Press the ‘+’ button of the Terminal window to proceed with the serial port connection setting.

The corresponding serial port is then connected as follows.

Now, run the code for ‘helloworld.c’ on the FPGA.

Click “Launch Hardware (Single Application Debug)” to program the Bitstream file and the “helloworld.c” code on the FPGA.

As shown in the following figure, if you enter decimal 777 in Terminal, a printf statement including the corresponding decimal is printed every second.