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MCU/SOC/FPGA Test Carrier B’d
Block Diagram of MCU/SOC/FPGA Test Carrier B’d
This carrier board is designed for testing new circuits (aka. Target B’d).
Testing the new Target B’d typically requires control signals from User. Depending on the test purpose and convenience, one of the following two types of control boards can be selected for testing :
① MCU SOM B’d
② FPGA / SOC SOM B’d
The structure of this carrier board will be explained based on the ZYNQ SOM B’d. (Refer to the schematics for MCU and other FPGAs)
1. Power Part
The carrier board receives 24V from an external source through a Barrel Jack connector and converts it to 12V / 5V / 3.3V via the Power Module. (The 24V is bypassed and output after passing through a Schottky diode.)
Case ① : FPGA / SOC SOM B’d
The FPGA / SOC SOM B’d receives operating power from Buck Converters 1-4.
These Buck Converters take 5V from the Power Module and generate the necessary voltages for the FPGA / SOC operation (1V, 1.8V, 1.35V, 3.3V).
Since the FPGA / SOC must follow a specific Power-On Sequence of Xilinx, the design ensures that each power supply turns on according to this sequence.
(ZYNQ’s Power-On Sequence: 1.0V → 1.8V → 1.35V → 3.3V)
These Buck Converters take 5V from the Power Module and generate the necessary voltages for the FPGA / SOC operation (1V, 1.8V, 1.35V, 3.3V).
Since the FPGA / SOC must follow a specific Power-On Sequence of Xilinx, the design ensures that each power supply turns on according to this sequence.
(ZYNQ’s Power-On Sequence: 1.0V → 1.8V → 1.35V → 3.3V)
Case ② : MCU SOM B’d
The MCU SOM B’d receives operating power from an SOM B’d LDO.
The LDO takes 5V from the Power Module and produces the 3.3V required for MCU operation.
2. ZYNQ PS Part
The ZYNQ PS MIO pins on the carrier board are connected to the TFT LCD, PS Reset SW, and PS User LED.
The purposes of these devices are as follows :
① TFT LCD
Allows graphing of data obtained from the New Target board.
② PS Reset SW
Used to reset the ZYNQ PS.
③ PS User LED
Indicates the operating status of the ZYNQ PS.
3. ZYNQ PL Part
The ZYNQ PL pins on the carrier board are connected to the PL User LED, Buzzer, User SW1-4, and User Slide SW.
The purposes of these devices are as follows :
① PL User LED
Indicates the operating status of the ZYNQ PL.
② Buzzer
Can be used for auditory confirmation of errors or notifications occurring during ZYNQ PL operation.
③ User SW1-4
Can be used when external input control is needed.
④ User Slide SW
Similarly, can be used when external input control is needed.
4. Connector Part
① FPGA / SOC SOM B’d Connector
Used when testing Target B’d with the FPGA / SOC SOM B’d as the control board.
② MCU SOM B’d Connector
Used when testing Target B’d with the MCU SOM B’d as the control board.
③ External I/O Connector
An expansion connector for additional elements required in Target B’d testing.
④ JTAG Tag-Connect Footprint
A footprint for using Tag-Connect’s Plug of Nail Programming Cable (supports JTAG).
⑤ FTDI JTAG Programmer B’d Connector
An M.2 Key-M Form Factor connector for mounting the JTAG Programmer B’d utilizing FTDI’s FT2232 IC.
⑥ Test Target B’d Connector
A mezzanine connector for mounting the test subject Target B’d.
Schematic of MCU / FPGA / SOC Test Carrier B’d (Rev.A)
PCB Artwork of MCU / FPGA / SOC Test Carrier B’d (Rev.A)
Verification of MCU / FPGA / SOC Test Carrier B’d (Rev.A)
MCU/SOC/FPGA Test Carrier B’dBlock Diagram of MCU/SOC/FPGA Test Carrier B’d1. Power PartCase ① : FPGA / SOC SOM B’dCase ② : MCU SOM B’d2. ZYNQ PS Part3. ZYNQ PL Part4. Connector PartSchematic of MCU / FPGA / SOC Test Carrier B’d (Rev.A)PCB Artwork of MCU / FPGA / SOC Test Carrier B’d (Rev.A)Verification of MCU / FPGA / SOC Test Carrier B’d (Rev.A)